Wednesday, September 12 - Morning

Regency Ballroom C&D - 8:30 a.m.

Opening Remarks: P.R. Mukund, General Conference Chair

Technical Program Overview:  John Chickanosky, Technical Program Chair

Keynote Address: Hiro Hashimoto, President and CEO, NEC Electronics, Inc.

Plenary Presentations:
ICs for Optical Communication,
Prof. Behzad Razavi, University of California at Los Angeles
HyperTransport Technology for Networking,
Peter Robinson, API NetWorks

12:30 p.m. OPEN LUNCH

Wednesday, September 12 - Afternoon

1:30 p.m. - 2:40 p.m.
Regency Ballroom C

W1.1:  VLSI Implementation of High Performance Burst Mode for 128-bit Block Ciphers, Y. Mitsuyama, Z. Andales, T. Onoye* and I. Shirakawa, Osaka University, Osaka, Japan and *Kyoto University, Kyoto, Japan

W1.2:  An Auditory Classifier Employing a Wavelet Neural Network Implemented in a Digital Design, J. Hughes, Rochester Institute of Technology, Rochester, NY

W1.3:  Performance Evaluation of 3rd Order Sigma-Delta Modulators Via FPGA Implementation, S.S. Abeysekera and C. Charoensak, Nanyang Technological University, Singapore

W1.4:  Light and Sound Data Fusion in Analog VLSI, M. Kanteti and A.H. Titus, Rochester Institute of Technology, Rochester, NY

1:30 p.m. - 2:40 p.m.
Regency Ballroom D

W2.1:  Current-Sensing for Crossbars, M. Sinha and W. Burleson, University of Massachusetts, Amherst, MA

W2.2:  Demonstration of Power Enhancements on an Industrial Circuit Through Delay Management of Non-Critical Data Paths, D. Velenis, K.T. Tang*, I.S. Kourtev**, V. Adler***, F. Baez**** and E.G. Friedman, University of Rochester, Rochester, NY, *Broadcom Corp., San Jose, CA, **University of Pittsburgh, Pittsburgh, PA, ***Sun Microsystems, Palo Alto, CA, and ****Intel Corp.

W2.3:  Efficient Gate Clustering for MTCMOS Circuits, M.H. Anis, M.K. Mahmoud and M.I. Elmasry, University of Waterloo, Waterloo ON, Canada

W2.4:  Gate-Diffusion Input (GDI) - A Novel Power Efficient Method for Digital Circuits: A Design Methodology, A. Morgenshtein, A. Fish* and I.A. Wagner**, Technion, Haifa, Israel, *Ben-Gurion University, Beer-Sheva, Israel, and **IBM Research Laboratory, Haifa, Israel

2:40 p.m.  BREAK

3:35 p.m. - 4:50 p.m.
Regency Ballroom C

W3.1:  ASIC and DSP Emplementation of Channel Filter for 3G Wireless TDD System, R. Veljanovski, J. Singh and M. Faulkner, Victoria University of Technology, Victoria, Australia

W3.2:  A Mobile Station Modem VLSI for CDMA2000-1x, S.-C. Han, T.H. Han, Y.-C. Kim, C.-J. Kim, K.-H. Lee, I.-K. Paik, K.-H. Kim, Y.-S. Kim and S.-W. Jung, Samsung Electronics, Kyunggi-Do, Korea

W3.3:  WCDMA Receiver Architecture with Unique Frequency Plan, M.A.I. Mostafa, M.C. Fernando, W.K. Chan and C. Gore, Texas Instruments, Dallas, TX

3:35 p.m. - 4:50 p.m.
Regency Ballroom D

W4.1:  Code Verification by Hardware Acceleration, H. Kohler, J. Kayser, H. Pape and H. Ruffner, IBM, Boeblingen, Germany

W4.2:  Vector Language:  A Proposed Verification Methodology for Intellectual Property Cores, A. Iniguez, Motorola, SPS, Tempe, AZ

W4.3:  The Use of SystemC for Design Verification and Integration Test of IP-Cores, A. Fin, F. Fummi and D. Signoretto, University of Verona, Verona, Italy

4:50 p.m. - 5:30 p.m.  RECEPTION
5:30 p.m. - 7:30 p.m.  PANEL DISCUSSION
“Solving the Validation Crisis”
Moderator: Graham Budd, ARM Limited