Thursday, September 13 - Morning

T1:  WIRELESS COMMUNICATIONS
8:55 a.m. - 10:30 a.m.
Regency Ballroom C

T1.1:  Algorithm, Architecture, and Implementation of Algorithmic Delay-Locked Loop Based Data Recovery Circuit for High-Speed Serial Data Communication, H. Song, Intel Corp., Chandler, AZ

T1.2:  A New 246MHz Active LC Band-Pass Filter for IF Sub-Sampling GSM Receivers, M.A.I. Elmala, M.A.I. Mostafa* and S.H.K. Embabi*, Texas A&M University, College Station, TX and *Texas Instruments, Austin, TX

T1.3:  A Low-Noise Fast-Settling Phase-Locked Loop with Extended Loop Bandwidth Enhancement by new Adaptation Techniques, Y. Tang, Y. Zhou*, S. Bibyk and M. Ismail, Ohio State University, Columbus, OH and *Motorola, Inc.

T1.4:  On-Chip RF Filters Using Bond Wire Inductors, M.A.I. Mostafa, J. Schland and S. Lazar, Texas Instruments, Dallas, TX

T2:  DIGITAL DESIGN METHODOLOGIES
8:55 a.m. - 10:10 a.m.
Potomac Rooms 5/6

T2.1:  Direct-Mapped Asynchronous Finite-State Machines in CMOS Technology, C. Sotiriou, Foundation for Research & Technology - Hellas (FORTH), Heraklion, Crete, Greece

T2.2:  A Socket Interface for GALS Using Locally Dynamic Voltage Scaling for Rate-Adaptive Energy Saving, T. Njolstad, O. Tjore, K. Svarstad, L. Lundheim, T.O. Vedal, J. Typpo, T. Ramstad, L. Wanhammar, E.J. Aas and H. Danielsen, Norwegian University of Science and Technology (NTNU), Trondheim, Norway

T2.3:  MCSoC:  A Platform for Clock Managed Systems on a Chip, I. Brynjolfson and Z. Silic, McGill University, Montreal, QU, Canada

T2.4:  Integrated Approach to Optimized Code Generation for Heterogeneous-Register Architectures with Multiple Data-Memory Banks, S. Fröhlich and B. Wess, Technische Universität Wien, Vienna, Austria


10:30 a.m. BREAK

T3:  CIRCUIT DESIGN & APPLICATIONS
10:55 a.m. - 12:35 p.m.
Regency Ballroom C

T3.1:  Input Controlled Refresh for Noise Tolerant Dynamic Circuits, A. Lakshmanan and R. Sridhar, University at Buffalo, Buffalo, NY

T3.2:  A Low-Phase-Noise CMOS Ring Oscillator with Differential Control and Quadrature Outputs,  L. Dai and R. Harjani, University of Minnesota, Minneapolis, MN

T3.3:  A Novel All Digital Phase Locked Loop (ADPLL) with Ultra Fast Lock Time and High Oscillation Frequency, K.-H. Cheng and Y.-J. Chen, Tamkang University, Taipei Hsien, Taiwan, R.O.C.

T3.4:  A Novel Impedance Control for USB2.0 Transceiver, K.-H. Koo, J.-H. Seo and J.-W. Kim, Samsung Electronics, Youngin, Korea

T4:  INTERCONNECT SOLUTIONS
10:55 a.m. - 12:35 p.m.
Potomac Rooms 5/6

T4.1:  A Stochastic Global Net-Length Distribution for a Three-Dimensional system-on-a-Chip (3D-SoC), J.W. Joyner, P. Zarkesh-Ha and J.E. Meindle, Georgia Institute of Technology, Atlanta, GA

T4.2:  A Practical Approach to DSM Repeater Insertion: Satisfying Delay Constraints while Minimizing Area and Power, A. Nalamalpu and W. Burleson*, Intel Corp., Hillsboro, OR and *University of Massachusetts, Amherst, MA

T4.3:  A New Two-Layer Power/Ground Router for VLSI Layout, J.C. Chi and M.C. Chi, Chung Yuan Christian University, Chung Li, Taiwan, ROC

T4.4:  Estimating Interconnect Wirelength for Soft IP, P. Hung, L. Séméria and M.J. Flynn, Stanford University, Stanford, CA


12:35 p.m. - 1:30 p.m. OPEN LUNCH

Thursday, September 13 - Afternoon

T5:  PROGRAMMABLE SYSTEMS & APPLICATIONS
1:30 p.m. - 3:10 p.m.
Regency Ballroom C

T5.1:  An Embedded Programmable Core for the Implementation of High Performance Digital Filters, B.I. Hounsell and T. Arslan, The University of Edinburgh, Edinburgh, Scotland

T5.2:  Cell Designs for Self-Timed FPGAs, C. Traver, R.B. Reese and M.A. Thornton, Mississippi State University, Mississippi State, MS

T5.3:  Reprogrammable Processing Capabilities of Embedded FPGA Blocks, T. Vaida, LSI Logic Corporation, Boulder, CO

T5.4:  Low-Power Constant-Coefficient Multiplier Generator, C.-Y. Pai, A.J. Al-Khalili and W.E. Lynch, Concordia University, Montreal, Quebec, Canada

T6:  LOW POWER MEMORY & CIRCUITS
1:30 p.m. - 3:10 p.m.
Potomac Rooms 5/6

T6.1:  Block-Based Multi-Period Refresh for Energy Efficient Dynamic Memory, J. Kim and M.C. Papaefthymiou, University of Michigan, Ann Arbor, MI

T6.2:  A Novel Low power CAM Design, G. Thirugnanam, N. Vijaykrishnan and M.J. Irwin, Pennsylvania State University, University Park, PA

T6.3:  On the Low-Power Design of DCT and IDCT for Low Bit Rate Video Codecs, N. August and D.S. Ha, Virginia Tech, Blacksburg, VA

T6.4:  An Improved Pass-Gate Adiabatic Logic, L. Varga, F. Kovacs and G. Hosszu, Technical University of Budapest, Budapest, Hungary


3:10 p.m.  BREAK

T7:  SOC/IP VALIDATION II & TEST GENERATION
3:35 p.m. - 5:15 p.m.
Regency Ballroom C

T7.1:  Reuse of Addressable System Bus for SOC Testing, S. Hwang and J.A. Abraham, The University of Texas at Austin, Austin, TX

T7.2:  Model Reduction Based on Value Dependency, H. Peng, Y. Moktari and S. Tahar, Concordia University, Montreal, QU, Canada

T7.3:  FSimGEO:  A Test Generation Method for Path Delay Fault Test Using Fault Simulation and Genetic Optimization, S. Yihe and *W. Qifa, Tsinghua University, Beijing, China and *Huawei Corporation of China, Shanghai, China

T7.4:  Design Verification and DFT for an Embedded Reconfigurable Low-Power Multiplier in System-on-Chip Applications, M. Margala, X. Chen*, J. Xu*, and H. Wang*, University of Rochester, Rochester, NY and *University of Alberta, Edmonton, AL, Canada

T8:  SYSTEM LEVEL DESIGN
3:35 p.m. - 5:15 p.m.
Potomac Rooms 5/6

T8.1:  A Flexible Approach to the Design of Complex Embedded Systems, J.M. Moya, F. Moya and J.C. Lopez, University of Castilla-La Mancha, Ciudad Real, Spain

T8.2:  Multi-Way Clustering Techniques for System Level Partitioning, M.L. Lopez Vallejo and J.C. Lopez Lopez, ETSI Telecomunicacion, Univ. Politecnica Madrid, Madrid, Spain

T8.3:  A Clustering Utility Based Approach for ASIC Design, S. Areibi, M. Thompson* and A. Vannelli*, University of Guelph, Guelph, ON, Canada, *University of Waterloo, Waterloo, ON, Canada

T8.4:  Structured Object Composition for System Modeling, V. Sinha, R. Gupta, University of California, Irvine, CA


4:40 p.m. - 6:00 p.m.  POSTER SESSION
6:30 p.m. - 8:00 p.m.  CONFERENCE BANQUET with Banquet Speech:
“Low Volume Manufacture of Chips, Boards, and Enclosures”
John Tanner, Tanner Research, Inc.
 

POSTER SESSION

P.1: An Efficient ABR Service Engine for ATM Network, Y. Choi, S. Kang* and S. Chong**, LG Electronics, Inc., Kumi, Korea, *Yonsei University, Seoul, Korea and **KAIST, Daejon, Korea

P.2: SoC Integration of Digital Audio Applications Using Protocol Compiler and Atmel FPSLIC, K. Feske, S. Mulka, J. Schneider and G. Heinrich, FhG IIS Erlangen, Dresden, Germany

P.3: A Low Power FIR Filtering Core, A.T. Erdogan, M. Hasan and T. Arslan, University of Edinburgh, Edinburgh, Scotland

P.4: A CMOS Dual-Modulus Prescaler Based on a New Charge Sharing Free D-Flip-Flop, S.-H. Yang, K.-C. Min and K.-R. Cho, Chungbuk National University, Cheongju, Korea

P.5: Optimum Sigma-Delta De-Modulator Filter Implementation Via FPGA, S.S. Abeysekera and C. Charoensak, Nanyang Technological University, Singapore

P.6: Modular Scalable Parallel Architectures for Fast Transforms, R.W. Johnson, L.A. Koyrakh and D.M. Pihl, MathStar, Inc., Minneapolis, MN

P.7: FPGA Prototyping of a Configurable USB Device SOC, N. Balachander and S. Chonnad, Synopsys, Inc., Mountain View, CA

P.8: Network Processor Design for Optical Burst Switched Networks, P. Mehrotra, I. Baldine*, D. Stevenson* and P. Franzon, North Carolina State University, Raleigh, NC and *MCNC

P.9: Testing for AMBA(TM) Compliance, A. Nightingale, ARM IP Solutions Division, S. York, United Kingdom

P.10:  IP Core Integrated and Platform Based System-On-a-Chip(SoC) Designs: An Application Perspective, T. Ramesh, IBM, Essex Junction, VT

P.11:  A Comparative Cost/Performance Evaluation of Digit-Serial Multipliers for Finite Fields of Type GF(2n), G. Bertoni, L. Breveglieri and *P. Fragneto, Politecnico di Milano, Milan, Italy and *ST Microelectronics, Agrate B., Italy

P.12:  A Unified Validation Methodology for System Level Co-Design and Co-Implementation, J. Goodenough, A. Bruce, A. Nightingale, P. Bates and G. Budd, ARM IP Solutions Division, S. York, United Kingdom

P.13:  A VLSI Design of a High-Speed Reed-Solomon Decoder, H. Lee, Agere Systems, Allentown, PA

P.14:  Dual Mode Transmitter with Adaptively Controlled Slew Rate and Impedance Supporting Wide Range Data Rates, H. Song, Intel Corporation, Chandler, AZ

P.15:  Circuit Challenges and Proposed Solutions Targeting Nanometer Technologies, R.M. Secareanu, M. Jones, M. Sadd, B. White and P. Maniar, Motorola SPS, Inc., Tempe, AZ

P.16:  A Dynamic Reconfigurable Clock Generator, R.M. Secareanu, D. Albonesi* and E.G. Friedman*, Motorola SPS, Inc., Tempe, AZ, *University of Rochester, Rochester, NY

P.17:  SCALIP - A Scalable IP Solution for Pipelined Arrays with Limited Feedback, M. Moe and H. Schmit, Carnegie Mellon University, Pittsburgh, PA

P.18:  Integrated Scheduling and Register Assignment for VLIW-DSP Architectures, T. Zeitlhofer and Bernhard Wess, Vienna University of Technology, Vienna, Austria

Thursday