Friday, September 14 - Morning

8:55 a.m. - 10:30 a.m.
Washington A

F1.1:  VLSI Reed Solomon Decoder Architecture for Networked Multimedia Applications, M. Martina, G. Masera, G. Piccinini, F. Vacca and M. Zamboni, Politecnico di Torino, Torino, Italy

F1.2:  A True Block Pipelined Programmable Reed-Solomon CODEC for High-Speed/Low-Power Applications, H.-J. Kwon, J.-S. Lee, S.-H. Lee and B.-Y. Jeong, Samsung Electronics, Kyunggi-Do, Korea

F1.3:  Digit-Serial Multiplier Design Using Skew-Tolerant Domino Circuits, S. Kim and G.E. Sobelman, University of Minnesota, Minneapolis, MN

F1.4:  An Efficient Digit-Serial Systolic Multiplier for Finite Fields GF(2m), C.H. Kim, S.D. Han and C.P. Hong, Taegu University, Kyungbuk, Korea

8:55 a.m. - 10:30 a.m.
Washington B

F2.1:  Reusable Memory Management System Design, S.K. Agun and M. Chang, Illinois Institute of Technology, Chicago, IL

F2.2:  A High-Speed Multi-Port Data Buffer Design for Low-Energy DSP Applications, S. Hong, State University of New York at Stony Brook, Stony Brook, NY

F2.3:  I/O Design Considerations for Multi-Application Circuits, T.L. Ruud and J.A. Wright, American Microsystems, Inc., Pocatello, ID

F2.4:  Sample Integrated Fourier Transform (SIFT): A Novel Real-Time DSP Process, W.E. Pelton, T.K. Ta*, N. Yossakda**, Faster Fourier Transforms, Fremont, CA, *Fujitsu Microelectronics, Santa Clara, CA and **Northwestern Polytechnic University, Fremont, CA

10:30 a.m. BREAK

10:55 a.m. - 12:35 p.m.
Washington Room A

F3.1:  CID/DRAM Mixed-Signal Parallel Distributed Array Processor, R. Genov and G. Cauwenberghs, Johns Hopkins University, Baltimore, MD

F3.2:  A New Sensing and Digital-Conversion Scheme with Adaptive Image-Quality Adjustment for a Fingerprint Sensor Chip, S. Shigematsu, H. Morimura and K. Machida*, NTT Lifestyle and Environmental Technology Laboratories, Kanagawa, Japan, *NTT Telecommunication Energy Laboratories, Kanagawa, Japan

F3.3:  Reducing the Cost of Scan in Deep-Sub-Micron Designs, K. Rahimi and M. Soma*, Redmond, WA and *University of Washington, Seattle, WA

F3.4:  IP Protection for VLSI Designs Via Watermarking of Routes, N. Narayan, R.D. Newbould, J.D. Carothers, J.J. Rodriguez and W.T. Holman*, The University of Arizona, Tucson, AZ and *Vanderbilt University, Nashville, TN

10:55 a.m. - 12:35 p.m.
Washington Room B

F4.1:  Re-Useable Hardware/Software Co-Verification of IP Blocks, A. Bruce and J. Goodenough, ARM IP Solutions Division, S. York, United Kingdom

F4.2:  Flexible IP Blocks for Customized Synthesis, M.M. Ziegler and M.R. Stan, University of Virginia, Charlottesville, VA

F4.3:  Design Methods for System-On-A-Chip Control CODECs to Enhance Reuse, J.S. Fisher and S.B. Bibyk, Ohio State University, Columbus, OH

F4.4:  A Hierarchical Simulation Framework for Application Development on System-on-Chip Architectures, V. Mathur and V.K. Prasanna, University of Southern California, Los Angeles, CA

12:35 p.m. - 1:30 p.m. OPEN LUNCH

Friday, September 14 - Afternoon

1:30 p.m. - 2:25 p.m.
Washington Room A

F5.1:  Noise-Aware Synthesis of Electrostatic Discharge Networks in Mixed-Signal Integrated Circuits, J. Lee, Y. Huh*, P. Bendix* and S.-M. Kang**, University of Illinois, Urbana, IL, *LSI Logic Corp., Milpitas, CA, and **University of California, Santa Cruz, CA

F5.2:  A Global Routing Methodology for Analog and Mixed-Signal Layout, K. Sajid, J.D. Carothers, J.J. Rodriguez and W.T. Holman, The University of Arizona, Tucson, AZ

F5.3:  Evaluating the Impact of Architectural-Level Optimizations on Clock Power, D. Duarte, V. Narayanan, M.J. Irwin and M. Kandemir, The Pennsylvania State University, University Park, PA

1:30 p.m. - 2:50 p.m.
Washington Room B

F6.1:  Future-Ready Ultrafast 8bit CMOS ADC for System-on-Chip Applications, J. Yoo, D. Lee, K. Choi and A. Tangel*, The Pennsylvania State University, University Park, PA and *University of Kocaeli, Yzmit, Turkey

F6.2:  A Low-Power Variable Resolution Analog-To-Digital Converter, C. Aust, R.S. Richmond* and D.S. Ha*, IBM Microelectronics, Research Triangle Park, NC and *Virginia Tech, Blacksburg, VA

F6.3:  A Low-Voltage Switched-Current Memory Cell Based Delta Sigma Modulator, A.S. Botha, P. Sniatala, K.W. Hsu and P.R. Mukund, Rochester Institute of Technology, Rochester, NY

F6.4:  Low-Voltage Switched-Current Circuits for Mixed Signal Systems, A. Handkiewicz, M. Lukowiak and M. Kropidlowski, Poznan University of Technology, Poznan, Poland